1. Field of the Invention
The present invention relates to a Bi-CMOS semi-conductor integrated circuit (IC) comprising bipolar (Bi) elements and complementary metal oxide semi-conductor (CMOS) elements, and more particularly to word-line drive circuits for driving the word lines of the memory cell array incorporated in a Bi-CMOS IC.
2. Description of the Related Art
A Bi-CMOS memory LSI, such as a SRAM (Static Random-Access Memory), comprises a memory cell array and a plurality of Bi-CMOS word-line drive circuits. The Bi-CMOS word-line drive circuits are arranged near the memory cell array and used to drive the word lines of the memory cell array at high speed.
FIG. 1 shows that one of the identical Bi-CMOS word-line drive circuits, designed to drive one of the word lines of the SRAM. The word-line drive unit comprises an NPN transistor Q1 for pulling up the word-line potential, an NPN transistor Q2 for pulling down the word-line potential, a P-channel MOS transistor TP for driving the pull-up NPN transistor Q1, an N-channel MOS transistor TN for driving the pull-down NPN transistor Q2, and two resistors R1 and R2. In FIG. 1, Vcc indicates the power-supply potential, Vss designates the ground potential, WL is one of the word lines of the memory cell array, and RD denotes a word-line selecting signal (i.e., a signal output by a decoder).
The conventional Bi-CMOS word-line drive circuit has bipolar transistors which are arranged at the rate of 1/2 piece per cell pitch of the memory cell array.
FIG. 2 is a plan view showing a part of an IC chip having a plurality of Bi-CMOS word-line drive circuits identical to that one shown in FIG. 1. More precisely, FIG. 2 shows that region in which one of the word-line drive circuits is formed and which includes the NPN transistor Q1 for pulling up the word-line potential.
FIG. 3 is a cross-sectional view taken along line 3--3 in FIG. 2. As can be understood from FIG. 3, said part of the IC chip comprises a semiconductor substrate 80 (a P-type silicon substrate), an N+ type buried layer 81 formed within the substrate 80, an N- type collector region 82 (an epitaxial layer) formed in the substrate 80 and on the buried layer 81, and a collector lead region 83 formed integral with the collector region 82 and connected to the buried layer 81.
The part of the IC chip further comprises a P- type intrinsic base region 84 (inner base region) formed in the surface of a portion of the collector region 82, a P+ type outer base region 85 formed in the surface of a portion of the collector region 82, an N+emitter region 86 formed in the surface of a portion of the inner base region 84, an element-isolating region 87 formed in the substrate 80 and isolating two bipolar transistors formed in the substrate 80, from each other, a field oxide film 88 formed in the surface of a portion of the substrate 80 and isolating the bipolar transistors, and an inter-layer insulating film 89 covering the surface of the entire substrate 80.
As is shown in FIG. 3, the inter-layer insulating film 89 has contact holes. An emitter line 91 made of metal extends through the first contact hole, contacting the emitter region 86 at one end and connected to a word line at the other end. A base line 92 made of metal extends through the second contact holes, contacting the outer base region 85. A collector line 93 made of metal extends through the third contact hole, contacting the collector lead region 83.
As is shown in FIG. 2, the emitter line 91 has a contact portion 71, the base line 92 has a contact portion 72, and the collector line 93 has a contact portion 73. In FIG. 2, a is the difference between half the width of each metal line and half the width of the contact hole, b is the width of each contact hole, c is the distance between the emitter line 91 and the base line 92, d is the width of the bipolar transistor Q1, e is the distance between the bipolar transistor Q1 and either adjacent bipolar transistor, f is the distance between the inner base region 84 and the element-isolating region 87, and g is the distance between the outer base region 85 and the collector line 93.
The width d of the bipolar transistor Q1 is determined by four factors--(i) the sum of the differences a, the width b of contact holes, the distance c between the liens 91 and 92, (ii) and the distance f between the regions 84 and 87 (i.e., microprocessing dimensions), (iii) the distance e between the bipolar transistor Q1 and either adjacent bipolar transistor, and (iv) the distance g between the outer base region 85 and the collector line 93.
In order to increase the storage capacity of the SRAM, the microprocessing dimensions are reduced, thereby reducing the size of the memory cells and the memory-cell pitch. Hence, the bipolar transistors of the word-line drive circuit must be arranged, at the rate of one or 1/2 piece per cell pitch. To this end it is necessary to decrease the width d of the bipolar transistor Q1. However, the width d can hardly be reduced, however. This is because the bipolar transistor Q1 has the element-isolating region 87, making it difficult to decrease the width d to the size of the memory cell.
In the case of 0.5 .mu.m design rule, for example, a=0.2 .mu.m, b=0.5 .mu.m, c=0.5 .mu.m, e=3.0 .mu.m, f=2.0 .mu.m, and g=1.0 .mu.m. The smallest value possible for the width d of the transistor Q1 is 9.2 .mu.m, that is, d=6a+3b+c+g+f+e=9.2 .mu.m.
The distance f is the width of an N-type isolating region located between the P-type regions 84 and 87, and the distance e is the width of the P-type isolating region 87 located between N-type regions. The N-type isolating region and the P-type isolating region 87 can have their widths f and e reduced by increasing their impurity concentrations. If their impurity concentrations are increased, however, the base-collector capacitance or collector-substrate capacitor of the bipolar transistor Q1 will increase, inevitably degrading the characteristic of the transistor Q1.
Even if the design rule is changed to one less than 0.5 .mu.m, e, f, and g remain unchanged. Hence, d cannot decrease below 6 .mu.m. Since the memory cells incorporated in a 4-MB SRAM has a length of about 5 .mu.m, it is next to possible to arrange bipolar transistors in the word-line drive circuit, each for every two memory cells --that is, at the rate of 1/2 piece per cell pitch.